1. Field of the Invention
The present invention relates to a time division switch used in digital exchange systems and particularly relates to a time division switch enabling effective execution of failure detection test for such time division switch.
2. Description of the Related Art
One of the most distinctive characteristics of the digital exchange system is its time division for exchange where one speech bus carries digital (PCM) signals by means of time division multiplexing. To exchange such digital signals, a digital exchange system comprises semiconductor devices such as memory switches and gate switches for message channels. Both of the memory switch and gate switch are widely and generally utilized applications of LSI technology. They are advantageous to obtain more economical systems of smaller size.
The message channel in a digital exchange system has, as a main component, a semiconductor device called "Time Division Switch" (Time switch or "TDSW"), which can input data to the time slots. The time switch comprises, for data replacement, memory devices capable of writing, storing and reading voice information bit strings. It is difficult from the viewpoint of engineering, however, to constitute a large scale digital message channel with a time switch alone, when considering the operation speed of such memory devices.
The time switch is an indispensable element in a message channel for a digital exchange system. It comprises speech path memories (hereinafter referred to as "SPM"), which are memory devices corresponding to the voice information bit strings as described above, speech path control memories (hereinafter referred to as "CTLM"), and a read/write address counter, and is provided with following functions.
An SPM stores digitally coded voice information on the data highway. The storage capacity of the SPM corresponds to the total number of time slots (channels) for the highways related to the time switch, i.e. the product of highway multiplexing and the number of highways. An CTLM is a memory to specify write and read addresses for the speech memory. The read/write address counter generates sequential addresses for sequential reading or writing of digitally coded voice information to be sent to the highway at the speech memory and control memory.
In an actual digital exchange, a plurality of highways from the transmission line are gathered to form a highly multiplexed highway, which is then connected to a time switch.
When the multiplexing of a time switch is 1024 (unit capacity for time switch), it is necessary for that time switch to make high speed processing with a memory cycle time of 60 ns in order for writing/reading within one time slot (122 ns). Recent advance in semiconductor technology has brought some memory devices ensuring a cycle time of not more than 60 ns, and solves this operation speed problem of memory devices. At present, time switches with multiplexing of 1024 (unit capacity for time switch) using write/read alternating method are adopted. Since one voice channel is coded in 8 bits, serial 8 bit data (contents at addresses 0 to 1023 in speech memory) are paralleled for multiplexing so that the number of channels to be sent in the same time period becomes eight times. Such paralleling is executed by a serial/parallel converter at the stage immediately before the switch. Thus, data exchange is executed with the speech memory of the time switch being also parallel.
As shown in FIG. 10, a time switch exists on a highway 708 (input side) with n channels. Serial data 702 where one frame with a cycle of 125 us has multiplexed data for n channels (One channel contains eight bits; it can be 16 bits at most) synchronizes with the output signal from an address counter 704 with a cycle of n for sequential writing to a speech memory 701 by means of a write circuit 703. In the speech memory 701, data are written corresponding to the addresses 1 to n (in this example, in the order from A to E). Then, the data A to E for n channels (t1 to tn) once stored in the speech memory 701 are, corresponding to the sequential addresses specified by a control memory 706 (n, 3, 2, . . . , 1 and n-1 in this example), read to the highway 708 (output side) by means of a read circuit 705. Thus, the n input channels and n output channels are switched. The control memory 706 contains correlations between the input time slots and output time slots.
In a conventional TDSW test method, a TDSW is supplied with a manually prepared test pattern from the test equipment instead of data input signals and write address signals from the connected microcomputer in normal operation, so that the results of TDSW processing for the test pattern are compared with the expected values stored in the test equipment.
Such conventional TDSW test method requires a time-consuming process to manually prepare the test pattern needed for the test. In addition, it is necessary to operate the test pattern to be input to the CTLM at a low speed as describe above, and the timing with the test pattern supplied to the SPM at a high speed must be also considered. Suppose, for example, a TDSW has multiplexing of 8K. In this case, reading at CTLM and SPM is made at the clock of 64 MHz, but writing to the CTLM is made at 8 MHz. Since one clock usually consists of one test pattern, eight test patterns are required to represent an 8 MHz clock. For writing to the CTLM in this TDSW with 8K multiplexing, 8.times.8K=64K of test patterns are required.
Further, the above test patterns must be supplied two to four times to improve the failure detection rate, which prolongs the time required for the test. Specifically, if 64K test patterns in the above example are supplied twice, the total number of patterns becomes 128K.